The continuing trend to fabricate semiconductor devices with smaller device features has led to some difficulties when trying to scale-down transistors that have a horizontal channel (hereinafter referred to as “horizontal channel transistors”). Two difficulties that can arise when trying to scale-down horizontal channel transistors are short channel effect and drain induced barrier lower (DIBL) effect. When a channel length of a transistor is reduced to 50 nanometers or less, the dispersion of device characteristics can become high due to fabrication process variations. When the channel length is 30 nanometers or less, the channel effect and DIBL effect can become so severe that the resulting transistor will operate abnormally.
Various different types of transistors have been developed to overcome some of the limitations associated with fabricating horizontal channel transistors. One such transistor is a double gate transistor. The double gate transistor includes a channel that may have a length of 30 nanometers or less, and a single gate on the channel or two gates on opposite sides of the channel. Because a conventional transistor has a gate electrode formed only over a horizontal channel, an electric field is asymmetrically applied to a top and bottom of the channel to prevent the turning on/off of the transistor from being controlled by the gate electrode.
In contrast, because a double gate electrode has two gate electrodes on opposite sides of a thin channel, an entire area of the channel is affected by the gate electrode. Thus, when the transistor is turned off, charge flow between a source and a drain may be suppressed to reduce power dissipation and to control the turning on-off of the transistor.
A double gate transistor using a damascene gate is disclosed in U.S. Patent Publication No. 2002/0177263 entitled “DAMASCENE DOUBLE-GATE MOSFET WITH VERTICAL CHANNEL REGIONS”, issued to Hussein et al.
FIG. 1 is a perspective view of a damascene double gate MOS transistor, such as that disclosed in U.S. Patent Publication No. 2002/0177263. As illustrated in FIG. 1, a transistor 14 includes a silicon layer 10 on an insulator 12 and a gate electrode 28 that extends across the silicon layer 10. A hard mask pattern 18 is on the silicon layer 10, and the gate electrode 28 is on the hard mask pattern 18. A gate insulator 30 is between the gate electrode 28 and a sidewall of the silicon layer 10. A source/drain region 22 is formed in the silicon layer 10 adjacent to opposite sides of the gate electrode 28.
As previously discussed, a double MOS transistor with a vertical channel has a narrow silicon layer in which a channel is formed. The gate may thereby exhibit a high controllability for the channel. Because a typical silicon layer has a width ranging from several nanometers to dozens of nanometers, the transistor is often called a fin field effect transistor (hereinafter referred to as “FinFET”) due to its shape. One difficulty in using FinFETs is that threshold voltages can vary considerably depending upon variations in their fabrication processes. Consequently, it can be difficult to control the threshold voltage of the transistor and provide cell uniformity in a high-density memory device.
Lowering of the threshold voltage of a transistor can increase the sub-threshold voltage leakage. Leakage current of a transistor results in degradation of the devices made therefrom. For example, leakage current can result in degradation of the data retention characteristics of a DRAM device. Consequently, it can be important to minimize leakage current of, for example, a source region to which a capacitor is connected. A channel concentration can be raised to increase a threshold voltage of the transistor. However, increased threshold voltage can cause a decrease in the turn-on current of the transistor, and increased channel concentration can cause an increase in junction current. Therefore, when such a transistor is used in a DRAM device, the decreased turn-on current can reduce a write margin, and the increased storage node junction leakage can deteriorate a data retention characteristic of the DRAM device.